Parallel Structure of GF (214) and GF (216) Multipliers Based on Composite Finite Fields
In this paper, a parallel VLSI structure of multipliers in GF (214) and GF (216) is pFesented. The proposed parallel structure is based on decomposition of the original finite fields. The parallel structures can complete the finite field multiplication in a few clock cycles at the cost of endurable increase of logic area. The mapping matrices between binary and composite field representations of GF (214) and GF (216) are presented, as well as the heuristic search algorithm. Two BCH decoders that are based on GF (214) and GF (214) and using the proposed parallel Galois multiplier structures are implemented on FPGA. Complexity and data throughput analysis shows that it is suitable for cases which require finite field multiplications with high data throughput, such as BCH decoders in DVB broadcasting and nand-flash memories.
Finite fields bit-parallel Galois multiplier composite fields heuristic search mapping matrix
Jianing Su Zhenghao Lu
Department of Electronics and Information Science, Soochow University, Suzhou, Jiangsu, 215006, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
830-833
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）