A Reconfigurable Linear Array Processor Architecture for Data Parallel and Computation Intensive Applications

摘要：

Recent embedded systems have switched, to parallel microprocessors. Linear array processors and 2-D array processors are two classifications for- the processing element (PE) interconnection. The former have better expansibility and greater throughput while the later have better communication efficiency. In order to improve the communication efficiency without losing expansibility, this paper introduces RLAP, a reconfigurable linear array processor architecture, targeted at data parallel and computation intensive applications in the video domain. Compared with the conventional linear array processors, the performance of RLAP improves by 8.7 times, 104％ and 10.8％ for the applications of 8×8 matrix transpose, 8×8 DCT and 16×16 SAD.

作者: Yucheng Liu Jing Xie Zhigang Mao

作者单位: Department of Microelectronics, Shanghai Jiao Tong University, Shanghai 200240, China Building of Microelectronics, No. 800, Dongchuan Road, Shanghai, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 853-856

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）