Characterization and Analysis of Pattern dependent Variation-aware Interconnects for a 65nm Technology
Pattern dependent interconnect physical parameter variations are studied based on a test . chip in 65 nm manufacturing process. The line width bias caused by etch process and the line thickness dishing and erosion caused by CMP process are modeled using electrical and physical measurements. New closed form models for R and C thus are derived. Simulation results show excellent agreement between measurements and new models. The variation impacts on R/C and thus Elmore delay and bandwidth also are investigated qualitatively and quantitatively using the analytical models.
Lele Jiang Xiaojing Qin Lifu Chang Yuhua Cheng
Shanghai Research-Institute of Microelectronics, Peking University, Shanghai 201203, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
921-924
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）