Design and Implementation of pipelined TMVP multiplier using block recombination
Fan and Hasan proposed a new scheme for subquadratic space complexity parallel multiplication in GF(2n) using Toeplitz matrix-vector products (TMVP). Recently, a recombined version of Fan-Hasan TMVP multiplier is also proposed to achieve lower space complexity. In this paper, optimal ending condition during recursion for the recombined multiplier is discussed. Based on the idea of decomposing building blocks, we present a new method to design pipelined parallel binary field multiplier which has subquadratic space complexity in combinational part and high throughput. ASIC results of this proposed multiplier are shown to have total area saving of 28.8％ with even better throughput against designs using brute force algorithm when optimized for speed.
Xiao Ma Guoqiang Bai
Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University. Beijing 100084, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
941-944
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）