A 12-bit 50-MSPS SHA-less Opamp-Sharing Analog-to-Digital Converter in 65nm CMOS

摘要：

This paper presents a 12-bit 50-MSPS pipelined Analog-to-Digital converter (ADC) in.a 65-nm 1P7M CMOS process. A hybrid time-sharing architecture without Sample-and-Hold Amplifier (SHA) is employed to make a trade-off between the performance and power consumption of the ADC. An SHA-less front-end is adopted, including a matched sampling network to considerably reduce aperture error between a 2.5-bit Multiplying Digital-to-Analog Converter (MDAC) and a Sub-Analog-to-Digital converter (SUBADC). Some efforts to optimize operational amplifier (opamp) are also made. Simulation results show that the ADC achieves 83.2-dB SFDR and 73.4-dB SNDR for input signal up to Nyquist range. The ADC consumes 26.6mW at sampling rate of 50MHz from 1.2-V supply voltage.

作者: Chen Shu Guanghua Shu Jun Xu Fan Ye Junyan Ren

作者单位: State Key Laboratory of ASIC and System, Fudan University State Key Laboratory of ASIC and System, Fudan University Micro-ZNano-Electronics Innovation Platfor

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 961-964

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）