Improved Algorithm for Pareto Front Computation for CMOS Op Amp Based on Multi-objective Genetic Optimization
The Pareto front permits the circuit designer to select optimal tradeoff from multiple performance objectives and received much attention in the analog design automation community recently. Now the dominant approach to find the Pareto front is through multi-objective genetic optimization, which requires large amount of computations since the embedding of a circuit simulator in the optimizing loop. We propose in this paper an improved algorithm for the Pareto front computation. By combing the analytical equation based optimization with the simulation based approach, the resulted two-stage algorithm accelerates the Pareto front seeking process significantly. The method is illustrated with the example of a Miller-compensated operational transconductance amplifier.
Peng Chen Yushun Guo
School of Electronics and Information Engineering, Hangzhou Dianzi University, Hangzhou 310018, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
1016-1019
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）