A Method to Build Reconfigurable Architectures by Extracting Common Subgraphs

摘要：

In this paper, we present a novel method to build reconfigurable architectures. Because an RTL description of a circuit can be converted to a data flow graph (DFG), our method is based on graph mining which aims to extract the common subgraphs among different benchmarks. A tool flow is proposed to convert benchmarks to data flow graphs and extract the common subgraphs. Benchmarks in the field of Error Checking and Correcting (ECC) are selected in the experiment to demonstrate that our method is correct and practical.

作者: Tianyun Zhang Rui Zhang Lingli Wang Yu Hu

作者单位: Software School, Fudan University, Shanghai 200433, China State Key Laboratory of ASIC & System, Fudan University, Shanghai 200433, China Electrical and Computer Engineering Department, University of Alberta, Canada

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 1043-1046

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）