A novel high-accuracy clock stabilizer with 50％ duty cycle

摘要：

This paper presents a novel synchronous 50％ clock duty cycle stabilizer (CDCS). The proposed circuit consists of a leading edge pulse generator, clock generator, charge pump loop and a pulse width extender. Leading edge pulse generator employs the edge of input clock as a starting pulse of the output clock to realize the synchronization. By utilizing the charge pump loop to control the discharging current in pulse width extender circuit, the output clock duty cycle converges to 50％ when CDCS reaches its stable state. The chip is designed and fabricated in TSMC 0.18μm 1P6M CMOS process. The core area is about 0.2 × 0.2mm. The circuit can stabilize an input clock with 10 to 125MHz frequency and 10％~90％ duty cycle.

作者: Biye Xu Lenian He

作者单位: Institute of VLSI design, Zhejiang University, Hangzhou 310027, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 1047-1050

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）