A 1.2-V 250-MS/s 8-bit Pipelined ADC in 0.13-μm CMOS

摘要：

This paper describes the implementation and experimental results of a 250 MS/s 8-bit pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS· process. The ADC uses a dedicated sample-and-hold amplifier (SHA) to achieve excellent linearity performances with high SFDR and very flat SNDR. Stage scaling in the pipeline chain is adopted to lower the power consumption. The ADC measures a SFDR of over 60 dB and 7.45 ENOB at 250 Ms/s with an input frequency of 19 MHz. SNDR only drops 1.7dB with input frequency increasing from dc to over 70MHz. Including all analog and digital blocks, the total power dissipation of the ADC is 60mW from a 1.2V power supply. The active area is 800 u.m><700 μm.

关键词： Analog-to-digital conversion CMOS analog integrated circuits sample-and-hold amplifier operational amplifier pipeline

作者: Peiyuan Wan Wei Lang Di Fang Wei Cui Pingfen Lin

作者单位: Beijing Embedded System Key Lab Beijing University of Technology Beijing, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 1059-1062

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）