A Novel RSD Correction for Pipeline ADC
Redundant signed digit (RSD) correction is widely employed in pipeline ADC. However, conventional RSD correction provides only one redundant bit to correct comparator offset voltage. This paper proposes a novel RSD correction with two redundant bits, which can correct larger offset voltage and improve the linearity of the pipeline stage transfer function. The effect of this RSD correction is verified in TSMC 0.18um 1P6M CMOS process. When the ADC works at 100MS/s conversion frequency and a 10MHz input signal is applied, the simulation result of SFDR is 105.9 dB.
Dawei Fu Lenian He Biye Xu
Institute of VLSI Design, Zhejiang University, Hangzhou, 310027, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
1063-1066
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）