A 4GS s3b wo-way ime-Interlea ed ADC in .13um C S
A time-interleaved ADC. 2 channels each consisting of a track-and-hold circuit with self-biased buffer and a 2GS/s flash ADC , is presented. The sub-ADC is composed of one-stage pre-amplifiers, latches and standard digital encoders with TSPC D-flip-flops. A half-reset latch is proposed to operate at sampling rate of 2GS/s with improved power consumption. 2.91b ENOB and 25.46dB SFDR are gotten by simulation at Nyquist frequency. The FoM of the ADC including T/H is 1.51 pJ/conv.-step.
Chunchen Gu i Zhao Zhiliang Hong
State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
1075-1078
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）