A Wide Lock-Range, Low Jitter Phase-Locked Loop for Multi-Standard SerDes Application

摘要：

A 0.8-3.6GHz Phase-locked loop (PLL) with quadrature outputs for multi-standard SerDes application is presented in this paper. To reach wide range output frequency, the lower output range is implemented by a divide-by-two operation on the upper output which is generated from a two-stage quadrant ring-VCO. Further more, adaptive bandwidth technique is applied to guarantee the stability of the loop. In addition, the process-dependent charge pump current mirrored from high precision bandgap reference circuit is used to cancel the bandwidth fluctuation from the process variation. The PLL is implemented in a 130nm digital CMOS process, while the core occupies 0.1mm2 and draws 5.1mA to 7.5mA current from 1.2V supply without yielding RMS jitter performance which is about 2.0ps.

作者: Shaolong Liu Hui Wang Yuhua Cheng

作者单位: Shanghai Research Institute of Microelectronics, Peking University, Shanghai, China, 201203

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 1091-1094

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）