A Low-Noise WCDMA Transmitter with 25％-duty-cycle LO Generator in 65nm CMOS

摘要：

This paper describes a 65nm CMOS low-noise WCDMA transmitter including direct quadrature voltage modulator and 25％-duty-cycle LO generator. In comparison with conventional approaches employing Gilbert mixers, the use of a passive voltage mixer, core of the transmitter, significantly improves the output noise and linearity performance. A divider directly generating 25％-duty-cyle LO is presented to drive the passive voltage mixer. Delivering 2dBm WCDMA output power at 2500 MHz. the transmitter achieves -44dBc ACLR at 5 MHz offset and -64dBc ACLR at 10 MHz offset, respectively. The noise floor at 2 dBm output is -163 dBc/Hz at the frequency offset above 40 MHz. The transmitter consumes a total power of 59 mW.

作者: Haiyi Wang Peichen Jiang Tingting Mo Jianjun Zhou

作者单位: Center of Analog/RF IC (CARFIC), Microelectronics, Shanghai Jiao Tong University, Shanghai 200240, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 1111-1114

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）