An Energy-efficient High-throughput Multi-rate QC-LDPC Decoder Supporting G.hn Applications
In this paper , an LDPC decoder fully compliant to the G.hn standard is presented. The decoder implements one kind of Layered Decoding Algorithm – turbo decoding massage passing (TDMP) algorithm for Quasi-Cyclic LDPC codes. A simple early termination strategy is presented to significantly increase the throughput and reduce the power consumption. Partially parallel architecture with an overlapped mechanism is proposed to improve the hardware efficiency. For the newly published standard G.hn, the uppermost expansion factor supported is 360 which is much larger than that in the 802.16e standard which brings higher throughput. In the architecture, look-up tables replace the permutation network to further reduce hardware complexity. Based on these methods, an LDPC decoder supporting the G.hn applications is implemented using a SMIC 130nm CMOS process. The decoder consumes 150 Kbits memory while achieving 1.54 Gbps throughput.
Hexi Hou Jun Ma Jiangpeng Li Guanghui He
School of Microelectronics Shanghai Jiao Tong University, Shanghai School of MicroelectronicsShanghai Jiao Tong University, Shanghai
国际会议
2011亚太信号与信息处理协会年度峰会(APSIPAASC 2011)
西安
英文
1-4
2011-10-18（万方平台首次上网日期，不代表论文的发表时间）