A Simple High-Efficient Inter-Core Communication Mechanism for Multi-Core Systems
(0) In this paper, we propose a simple and high efficient inter-core communication mechanism for multi-core systems. To alleviate the high hardware complexity and low communication efficiency originated from the relatively independent processor and NoC designs, we propose a scheme that integrates the computation and communication together as an efficient system. The space of the register file is extended using a configurable logic, to reduce the possibility of memory accesses without increasing operand space. Furthermore, read and write ports of synchronous FIFOs that used as interfaces between processors and network routers are mapped to register file address space by an added configure instruction, so that the calculation results from computing units can be shared highly efficiently between different cores. Also, for each single core, we adopt SIMD technology to enhance performance of processing multimedia and communication applications. The system is synthesized to achieve 830MHz under 65nm TSMC technology in typical case.
Heng Quan Ruijing Xiao Kaidi You Bei Huang Xiaoyang Zeng Zhiyi Yu
State Key Laboratory of ASIC and System, Fudan University, Shanghai
国际会议
2011亚太信号与信息处理协会年度峰会(APSIPAASC 2011)
西安
英文
1-5
2011-10-18（万方平台首次上网日期，不代表论文的发表时间）