Architectures For 3780 Point FFT Processor
3780 point FFT processor is the key component in DTMB receiver. It is generally implemented by decomposing 3780 point to small size, which can be implemented with WFTA and PFA in pipelined architecture. Several architectures were proposed and patented, the differences of the architectures lie in the way 3780 are decomposed and the processing order of small sized WFTA module. In this paper, the architectures for 3780 point FFT processor are analyzed, and the architectures with different processing order and internal wordlength are modeled with Matlab and simulated, the simulation results shows that processing larger sized WFTA at Grst stages can achieve better performance, and the varied decomposition and processing order can achieve varied performance in terms of SQNR and hardware cost.
3780 point FFT WFTA PFA
He Jing Li Tianyue Xu Xinyu
Information Engineering School, Communication University of China Beijing, China
国际会议
2011 4th International Congress on Image and Signal Processing(第四届图像与信号处理国际学术会议 CISP 2011)
上海
英文
2549-2552
2011-10-15(万方平台首次上网日期,不代表论文的发表时间)