Modified Reduced Delay BCD Adder

摘要：

Current trends in the academia and industry is managing and processing a high volume of data. Most of the time is spend on converting the data from decimal to binary, processing and converting back to decimal. The direct production of decimal sum offers a significant improvement in addition over methods requiring decimal correction. Here is the proposition which will reduce the conversion and processing time. This work is the extension of Alp Arslan Bayracci and Ahmet Akkas et al of reduced delay Binary Coded Decimal (BCD) adder. In some corner case, adder design was misbehaving and has been corrected and presented.

关键词： Adder Higher Valence adder Carry lookahead adder decimal adder BCD Adder

作者: Sundaresan C Chaitanya CVS PR Venkateswaran Somashekara Bhat Mohan Kumar J

作者单位: MCIS,Manipal University Manipal, India MCIS,Manipal UniversityManipal, India WRI, BHEL Tiruchirappali, India MIT, Manipal University Manipal, India MCIS, Manipal University Manipal, India

会议类型: 国际会议

会议名称: 2011 4th International Conference on Biomedical Engineering and Informatics(第四届生物医学工程与信息学国际会议 BMEI 2011)

会议地点: 上海

会议语种:英文

页码: 2161-2164

在线出版日期: 2011-10-15（万方平台首次上网日期，不代表论文的发表时间）