Efficient Residue Checker Using New Binary Modular Adder Tree Structure For Error Detection of Arithmetic

摘要：

An error residue checker for MAC circuit is proposed. By introducing SD number system into error detection arithmetic, an efficient SD residue checker can be implemented. In this paper, by introducing two kinds of modulo mm = 2P± 1) adders, an efficient modulo m binary adder tree is proposed which is used to implement modulo m multiplier(MSDM) and binary-to-residue converter based on SD number arithmetic. By using the presented residue arithmetic circuits, the error detection can be performed in real-time for a large productsum circuit.

作者: Mingda Zhang Shugang Wei

作者单位: Department of Production Science and Technology, Gunma University Ota-shi,Gunma,Japan 373-0057

会议类型: 国际会议

会议名称: 2011 Eighth International Conference on Fuzzy System and Knowledge Discovery(第八届模糊系统与知识发现国际会议 FSKD 2011)

会议地点: 上海

会议语种:英文

页码: 2478-2482

在线出版日期: 2011-07-26（万方平台首次上网日期，不代表论文的发表时间）