A Co-Design Method for Parallel Image Processing Accelerator based on DSP and FPGA

摘要：

In this paper, we present a co-design method for parallel image processing accelerator based on DSP and FPGA. DSP is used as application and operation subsystem to execute the complex operations, and in which the algorithms are resolving into commands. FPGA is used as co-processing subsystem for regular data-parallel processing, and operation commands and image data are transmitted to FPGA for processing acceleration. A series of experiments have been carried out, and up to a half or three quarter time is saved which supports that the proposed accelerator will consume less time and get better performance than the traditional systems.

关键词： Image processing accelerator co-design method parallel architecture coprocessor

作者: Ze Wang Kaijian Weng Zhao Cheng Luxin Yan Jing Guan

作者单位: aState Key Lab. of Multi-spectral Information Processing Technology, Inst. for Pattern Recognition & Institute of Manned Space System Engineering, CAST, Beijing, 100094

会议类型: 国际会议

会议名称: 第七届多光谱图象处理与模式识别国际学术会议

会议地点: 桂林

会议语种:英文

页码: 1-6

在线出版日期: 2011-11-01（万方平台首次上网日期，不代表论文的发表时间）