Application of Fault Simulation Test in the VLSI Failure Analysis
Purpose of VLSI failure analysis is to find effective measure to eliminate or reduce the same failure to happen again. But failure mechanism or failure mode of VLSI is variety. If the VLSI failure analyzer can not find out the root cause, wrong prevention method may be adapted and failure may still happen next time. This paper introduces fault simulation test, which is an effective way to distinguish the similar failure mechanism and confirm the failure mode, such as latch-up effect, electric over stress (EOS), etc. It can provide useful reference information for the users or producers. At the same time, several typical failure analysis cases are used to show how the fault simulation test works.
fault simulation test failure analysis latch-up contamination
Xiaoling LIN Qingzhong XIAO Ruohe YAO
National Key Laboratory of Science and Technology on Reliability Physics and Application of Electric Institute of Microelectronics Schoolof Electron and Information Engineering South China University o
国际会议
西安
英文
329-332
2011-06-17（万方平台首次上网日期，不代表论文的发表时间）