Design of Bit Error Rate Tester Based on a High Speed Bit and Sequence Synchronization
In traditional BER ( Bit Error Rate) tester, bit synchronization applied digital PLL and sequence synchronization utilized sequences correlation.lt resulted in a low speed on bit and sequence synchronization, this paper came up new method to realize bit and sequence synchronization .which were Bit-edge-tracking method and Immittingsequence method.The BER tester based on FPGA was designed.The functions of inserting error-bit and removing the false sequence synchronization were added. The results of Debuging and simulating display that the time to realize bit synchronization is less than a bit width,the lagged time of the tracking bit pulse is 1/8 of the code cycle,and there is only a M sequences cycle to realize sequence synchronization.This new BER tester has many advantages,such as a short time to realize bit and sequence synchronization.no false sequence synchronization,testing the ability of the receiving ports error-correcting and a simple hareware.
BER tester M sequence genetator PLL Inserting error-bit s bit synchronization sequence synchronization
Wang Xuanmin Zhao Xiangmo Zhang Iichuan Zhang Yinglong
School of Information Engineering Chang an University Xian, China
国际会议
重庆
英文
379-383
2011-01-21（万方平台首次上网日期，不代表论文的发表时间）