Multipurpose quick 3D packaging process
A novel small-sized chip circuit auxiliary layer (SCCAL) multipurpose 3D package process in order to solve the problem of shortages in flexibility and diversity of the traditional through-silicon via (TSV) process is presented in this paper. It meets the requirement of large amount of silicon dies which need connecting together by TSV technology but were designed respectively that wafers were processed without via holes drilling. This process involves a small-sized chip circuit auxiliary layer which is used as a carrying base and connecting auxiliary layer. Also, an improved TSV technology is involved that via holes could be produced through the PADs in the silicon dies. It is verified that, the whole process time of 3D packaging process is shortened drastically and the flexibility of the 3D packaging is greatly improved.
Zhao Yongrui Ma hongbo Bi Minglu Huang Zhanwu Jia Jun Lai Xinquan
Institute of Electronic CAD, Xidian University, Xian, Shaanxi 710071, PR China China Electronics Technology Group Corporation The 54th Research Institute, Shijiazhuang, Hebei, 050 Key Lab of High-Speed Circuit Design and EMC, Ministry of Education, Xidian University, Xian, Shaan
国际会议
2011 International Symposium on Advanced Packaging Materials(2011年先进电子封装材料国际会议APM)
厦门
英文
287-290
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）