Formal verification of embedded systems using the Alvis approach
Embedded systems are usually characterized by timecritical reactions and increased complexity. Because it is usually impossible to correct a system bug by simply uploading of a new version of a system software or firmware, a system behavior should be verified in a formal manner. The Alvis approach presented in this paper is able to verify the system behavior, by specifying the border between a developed embedded system and its environment. The means to move the border is then proposed, which allows the designer to create a formal representation for selected parts of a model only.
embedded systems formal verification graphical modelling
Leszek Kotulski Marcin Szpyrka
AGH University of Science and Technology, Mickiewicza 30, Krakow, Poland
国际会议
Fourth International Conference on Advanced Design and Manufacturing(第四届先进设计与制造国际会议)
昆明
英文
209-212
2011-09-21（万方平台首次上网日期，不代表论文的发表时间）