会议专题

REDUCING CACHE CONTENTION OF L2 SHARED CACHE ON MULTI-CORE PROCESSOR ARCHITECTURE

The multi-level cache hierarchy has long been adopted in microprocessors to deal with the memory wall problem.Nevertheless, contention misses and data thrashing in the shared LLC may still hurt performance due to interference between multiple threads running on the same processor.Based on applications temporal reuse behavior, we propose a Reuse Frequency based Filter (RFF) algorithm to select possible reused data from replaced data, reducing harmful displacement of useful data and data thrashing of the shared LLC on a chip Multi-Processor (CMP) architecture.Our simulation results show that the proposed mechanism can effectively reduce harmful replacements and cache conflicts by 19.7% and increase IPC of programs by 1.68% on average.

Multi-level cache Cache contention Multi-core Cache thrashing Shared cache

LIMIN HAN DEYUAN CAO LIWEN SHI JIANFENG AN

Department of Computer Science and Engineering Northwestern Poly technical University Xian 710072,China

国际会议

3rd International Conference on Mechanical and Electrical Technology(ICMET2011) (2011第三届机械与电气技术国际会议)

大连

英文

437-441

2011-08-26(万方平台首次上网日期,不代表论文的发表时间)