On a Gate Sizing Of Multiple-paths Circuit For Optimizing Power-delay
Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. In the previous work 1, the method of optimizing power-delay efficiency in a logical path showed about 40％ greater efficiency in power dissipation than the existing technique 2. However, our previous technique 1 is constrained for a single logical path. In this paper, we extend it for a multiple logical paths and thus, determine the gate size according to the formula derived in this paper.
Logical Effort capacitive transformation equation equal delay model multiple paths gate sizing power-delay efficiency
Seung Ho Lee Jong Kwon Chang
Department of Electrical Engineering,University of Ulsan,Korea
国际会议
The 6th International Forum on Strategic Technology(IFOST 2011)(第六届国际战略技术论坛)
哈尔滨
英文
637-642
2011-08-22（万方平台首次上网日期，不代表论文的发表时间）