Design of High-speed Sampling Circuits

摘要：

As high-speed signal sampling is not easy to achieve and sampled high-speed data is not easy to accept or control, two methods of high-speed sampling clock generation and clock distribution are given relating to practical application. Two ways of high-speed data deceleration are introduced, namely the hardware multiplexer transition method and the software programming control method by large scale integrated circuit. The sampling circuit can handle the data at the highest sampling rate of 3GHz. The systems have the quality of high integration, low power consumption, simple structure and excellent performance. All the programs have been proven feasible and achieving good results.

关键词： high-speed ADC clock distribution DEMUX FPGA

作者: Hao Lu Zhenzhan Wang Guoxing Gao

作者单位: Center for Space Science and Applied Research, Chinese Academy of Sciences Graduate University of C Center for Space Science and Applied Research, Chinese Academy of Sciences, Beijing, China Navy Submarine Academy,Qing Dao, China

会议类型: 国际会议

会议名称: 2011 International Conference on Electronic & Mechanical Engineering and Information Technology(EMEIT 2011)(2011年机电工程与信息技术国际会议)

会议地点: 哈尔滨

会议语种:英文

页码: 4516-4519

在线出版日期: 2011-08-12（万方平台首次上网日期，不代表论文的发表时间）