A Fast Virtual Device Framework for Improving RTL Verification Efficiency
Functional verification is time-consuming in design of processors. In order to rapidly build a reference model and automatically compare simulation resulting, this paper proposes a virtual device framework based full system simulator. The framework can speed up construction of verification environment for processors, from internal components to full processors. We demonstrate the method using the decoder component verification in Longteng Cl processor. The result shows the framework is efficient.
virtual device functional verification full system simulator
Jianfeng An Xiaoya Fan Shangang Zhang
Department of Computer Science and Engineering Northwestern Polytechnical University Xian 710072, China
国际会议
西安
英文
73-75
2011-05-13（万方平台首次上网日期，不代表论文的发表时间）