A High Performance Hardware Implementation Image Encryption With AES Algorithm
This paper describes implementation of a high-speed encryption algorithm with high throughput for encrypting the image. Therefore, we select a highly secured symmetric key encryption algorithm AES (Advanced Encryption Standard), in order to increase the speed and throughput using pipeline technique in four stages, control unit based on logic gates, optimal design of multiplier blocks in mixcolumn phase and simultaneous production keys and rounds. Such procedure makes AES suitable for fast image encryption. Implementation of a 128-bit AES on FPGA of Altra company has been done and the results are as follow: throughput, 6 Gbps in 471 MHz. The time of encrypting in tested image with 32.32 size is 1.15ms.
Advanced Encryption Standard(AES) Pipelining, Image Encryption Decryption.
Ali FARMANI MohamadJafari SeyedSohrabMiremadi
University of Tabriz
国际会议
Third International Conference on Digital Image Processing(ICDIP 2011)(第三届数字图像处理国际会议)
成都
英文
24-30
2011-04-15（万方平台首次上网日期，不代表论文的发表时间）