会议专题

Parallel of low-level computer vision algorithms on a multi-DSP system

Parallel hardware becomes a commonly used approach to satisfy the intensive computation demands of computer vision systems. A multiprocessor architecture based on hypercube interconnecting digital signal processors (DSPs) is described to exploit the temporal and spatial parallelism. This paper presents a parallel implementation of low level vision algorithms designed on multi-DSP system. The convolution operation has been parallelized by using redundant boundary partitioning. Performance of the parallel convolution operation is investigated by varying the image size, mask size and the number of processors. Experimental results show that the speedup is close to the ideal value. However, it can be found that the loading imbalance of processor can significantly affect the computation time and speedup of the multi-DSP system.

Parallel architecture Computer vision Image processing Parallel DSP

Huaida Liu Pingui Jia Lijian Li Yiping Yang

Research Center of Integrated Information System Institute of Automation, Chinese Academy of Science The National Engineering & Technology Research Center for ASIC Design Institute of Automation, Chine

国际会议

Third International Conference on Digital Image Processing(ICDIP 2011)(第三届数字图像处理国际会议)

成都

英文

231-236

2011-04-15(万方平台首次上网日期,不代表论文的发表时间)