An Improved Voltage-Controlled Delay Line For Delay Locked Loops

摘要：

This paper presents a new voltage controlled delay line (VCDL) for a 30-phase 500MHz DLL. The new VCDL circuit solves the problem of flicker noise caused by the tail current source. The post-simulation result indicates that the VCDL has moderate linearity range, low Processing-Voltage-Temperature (PVT) sensitivity and good noise resistance. It can be perfectly applied in the 5Gbps Over-sampling based Clock and Data Recovery (CDR) circuit.

关键词： voltage controlled delay line phase noise Clock and Data Recovery circuit delay-locked loop

作者: Gang Luo Xianjun Zeng

作者单位: School of Computer Science National University of Defense Technology Changsha, Hunan,China

会议类型: 国际会议

会议名称: 2011 3rd IEEE International Conference on Computer Research and Development(ICCRD 2011)(2011第三届计算机研究与发展国际会议)

会议地点: 上海

会议语种:英文

页码: 237-240

在线出版日期: 2011-03-11（万方平台首次上网日期，不代表论文的发表时间）