A BIST Scheme based on Resistance Match for Current-Mode R-2R Ladder Digital-to-Analog Converter
This paper presents a Built-in Self-Test (BIST) scheme and its implementation for a current-mode R-2R ladder Digital-to-Analog Converter (DAC). The technique is based on the resistance match of the R2R ladder in DAC. With the extra Design for Testability (DFT) circuits, test constant current follows into two resistance-matched branches, and the voltage drops on two branches of the resistor ladder change the voltage values at the inputs of the operational amplifier, which works as a comparator in the test mode. The output of the operational amplifier is employed for fault detection through a window comparator, which creates a pass/fail signature signal. The circuit-level simulation and experimental results of the BIST system for a 8-bit DAC in standard CMOS 0.18-fim technology are presented to demonstrate the feasibility of the proposed BIST scheme with fault coverage of 96％ and area overhead of approximately 6％.
design for testability digital-to-analog converter biult-in seft-test DAC-under-test
Yuan Jun Tachibana Masayoshi
Electronic and Photonic System Engineering Kochi University of technology Kami-City,Kochi,Japan
国际会议
上海
英文
305-309
2011-03-11（万方平台首次上网日期，不代表论文的发表时间）