Efficiency Improvements For A Speech Recognition Coprocessor

摘要：

This paper proposes a revised MSAC (Multiplier Square Accumulate Calculation) coprocessor called VPD3010, which is used to calculate Mahalanobis distance for ASR (Automatic Speech Recognition). We improved the address generating unit to provide frame-increment and resetting function, and appended feedback signal as an output port, which could be used as interrupt trigger or query signal by the main processor. Design of VPU3010 was verified on Xilinx FPGA platform firstly, then has been implemented on 0.1811 m UMC technology. Experiments show that the real-time factor of system based on VPU3010 working at 50MHz is 0.72 compared with 0.82 of MSAC at SOMHz, which could significantly improve the efficiency of the C-Program calling the coprocessor.

关键词： ASR embedded system ARM co-processor

作者: Hui Geng Weiqian Liang Ming Dong Runsheng Liu

作者单位: Beijing VoiceOn Technology Co. Ltd.,Beijing 100084,China Dept. of Electronic Engineering,Tsinghua Univ.,Beijing 10084,China

会议类型: 国际会议

会议名称: 2011 3rd IEEE International Conference on Computer Research and Development(ICCRD 2011)(2011第三届计算机研究与发展国际会议)

会议地点: 上海

会议语种:英文

页码: 336-339

在线出版日期: 2011-03-11（万方平台首次上网日期，不代表论文的发表时间）