20 MS/s, 1.6 mW, 50dB SFDR Switched-Capacitor DAC

摘要：

This paper presents a 1.6mW, 20 MS/s DAC with 0.33 pJ/conversion-step figure-of-merit, effective number of bits exceeding 7.9 and 0.40mm2 total chip area. A new variety of the non-binary series allowed design of the switched-capacitor charge pump array, with switched capacitance 7.3 pF, maximum to minimum capacitance ratio 7.2 and 7 matched capacitors, resulting in compact DAC layout. The proposed device was implemented in the 0.18um TSMC CMOS technology.

关键词： Digital-analog conversion Switched capacitor circuits

作者: Oleg Nizhnik Kohei Higuchi Kazusuke Maenaka Takashi Ooshima

作者单位: Maenaka Human-sensing Fusion Project ERATO project group of JST Himeji,Japan

会议类型: 国际会议

会议名称: 2011 3rd IEEE International Conference on Computer Research and Development(ICCRD 2011)(2011第三届计算机研究与发展国际会议)

会议地点: 上海

会议语种:英文

页码: 340-344

在线出版日期: 2011-03-11（万方平台首次上网日期，不代表论文的发表时间）