A Monolithic 0.18 urn CMOS Frequency Synthesizer for WLAN 802.11a Application
Based on the transceiver architecture of WLAN 802.11a, the frequency plan of the RF transceiver is accomplished. A PLL (phase-locked loop)-rype frequency synthesizer used for the system has been implemented in the standard 0.18-um mixed-signal and RF 1P6M CMOS technology of SMIC. It integrates a VCO, a dual-modulus prescaler, PFD, a charge pump, a control logic, various digital counters and digital registers onto a single chip. With the help of the linear model of the loop, the design and optimization of the loop parameters are discussed in detailed. The measured results show that the locked range was 40964288 MHz and the phase noise could reach -117.3 dBc/Hz at 1 MHz offset from the carrier 4.154 GHz, the output power is about -3 dBm. The chip area is 0.675 mm X 0.700 mm. The DC power consumption of the core part is about 24 mW under one 1.8-V supply.
frequency synthesizer PLL VCO prescaler PFD CP phase noise
Wu Xiushan Huan Changhong Chen Zhiqiang Wang Li Pan Lanfang
College of Electrical & Mechanical Engineering of China Jiliang University Hangzhou,China
国际会议
上海
英文
434-438
2011-03-11（万方平台首次上网日期，不代表论文的发表时间）