FPGA Implementation of Tierl Coding for JPEG2000

摘要：

The tierl coding in JPEG2000 contains two coding blocks, the bit plane coding and arithmetic coding, which are all heavy computation and suitable for hardware implementation. The architectures for bit plane coding and arithmetic coding are designed and combined together to implement the tierl coding. The verilog HDL modules for tierl coding are programmed, simulated and synthesized to Alteras FPGA. The generated programming file is then downloaded to FPGA, the Alteras embedded logic analyzer, named Signal-Tap II, is used to debug the system, the result shows that the architectures designed in this paper are correct

关键词： JPEG2000 Tierl coding Bit plane Coding arithmetic coding FPGA

作者: Shijie Qiao Jinqian Sai Yong Gao Yuan Yang

作者单位: Department of Electronic Engineering Xian University of Technology Xian,China

会议类型: 国际会议

会议名称: 2011 3rd International Conference on Computer and Network Technology(ICCNT 2011)(2011第三届IEEE计算机与网络技术国际会议)

会议地点: 太原

会议语种:英文

页码: 591-593

在线出版日期: 2011-02-26（万方平台首次上网日期，不代表论文的发表时间）