The High Speed Accomplishment of DES and 3DES Algorithm Based on FPGA and its research

摘要：

A high speed accomplishment of DF.S and 3DES algorithm based on FPGA is given in this paper. The design adopted the way to achieve the whole pipeline, which improves the systems operating frequency greatly. The procedure is as follow: modeling for Verilog Hardware Description Language(VHDL) implementation, functional simulation, getting the results, downloading to FPGA.

关键词： DES/3DES FPGA whole pipeline high-speed implementation

作者: Bo Yin Wei Yang Jiajia Dong Guang Yang

作者单位: College of Information Science and Engineering,Ocean University of China,Qingdao,China Department of Computer Sciences and Technology,Qingdao University of Science & Technology,Qingdao,Ch

会议类型: 国际会议

会议名称: 2011 3rd International Conference on Computer and Network Technology(ICCNT 2011)(2011第三届IEEE计算机与网络技术国际会议)

会议地点: 太原

会议语种:英文

页码: 530-532

在线出版日期: 2011-02-26（万方平台首次上网日期，不代表论文的发表时间）