A Simulation of Improved Synchronizer
In digital circuit systems, metastability often occurs in data transmission in defferent clock domains. The core of this thesis is how to deal with these problems and avoid the occurrence of metastable state effectively, in order to make the system transfer effectively. Based on some existing synchronizer, an improved synchronizer is proposed in this paper to increase the mean time between failures (MTBF) effectively. Functional simulation by H-Spice and relative data analysis show that the improved synchronizer has a better performance and longer MTBF than cascade synchronizer and synchronizer of using redundant flip-flops and masking.
metastablility synchronizer MTBF
Zhuo Bi Yijun Dai Meihua Xu
Micro-electronic R&D Center,Shanghai Univ Shanghai,China School of Mecha.Engin.and Automation,Shangh School of Mecha.Engin.and Automation,Shanghai Univ Shanghai,China
国际会议
太原
英文
145-149
2011-02-26（万方平台首次上网日期，不代表论文的发表时间）