A compiler for Ladder diagram to multi-core dataflow architecture
Multi-core and dataflow architecture recently researched on parallel computing can well satisfy the requirement of high-performance for PLC processors handling program by exploiting parallelism in the program. But the compiler translating the ladder diagram program into the instructions of the architecture has not been yet developed. For the problem, the paper presents a compiler aiming at editing a ladder diagram which is one of programming languages of PLC and then compiling it into instructions of multi-core function-level dataflow architecture. The compiler takes row doubly linked list as internal representation of a ladder diagram, and logic binary- tree as intermediate representation during the process of compiling according to similarity of the binary tree to function-level dataflow graph, written in Java.
PLC ladder diagram multi-core dataflow function-level compiler
Jiarong Guo Zhuo Bi Feng Ran Meihua Xu
Microelectronic R&D Center,Shanghai University Shanghai,China School of Mechatronical Engineering and Automation,Shanghai University Shanghai,China Microelectronic R&D Center,Shanghai UniversityShanghai,China
国际会议
太原
英文
347-351
2011-02-26（万方平台首次上网日期，不代表论文的发表时间）