Research and Implementation of A High-speed Reconfigurable Grain Algorithm

摘要：

A high-speed and dynamic reconfigurable hardware architecture of Grain algorithm is presented.which can satisfy the different characteristic of Grain-80 and Grain-128 algorithm.To save the hardware cost and get shorter critical path,we proposed tree network to implement LFSR and ISLFSR.As to the different highspeed method,this paper perform detailed comparison and analysis.placement and routing of reconfigurable design have accomplished on 0.18μm CMOS process,the result proves the critical throughput can achieve 10Gbps.

关键词： High-speed Reconfigurable Feedback shift register

作者: Zhongxiang Chang Zibin Dai Wei Li Bang Liu

作者单位: Zhengzhou Information Science and Technology Institute Zhengzhou,China

会议类型: 国际会议

会议名称: 2011 3rd International Conference on Computer and Network Technology(ICCNT 2011)(2011第三届IEEE计算机与网络技术国际会议)

会议地点: 太原

会议语种:英文

页码: 19-22

在线出版日期: 2011-02-26（万方平台首次上网日期，不代表论文的发表时间）