SAT-Based Test Generation for Transition Path Delay Faults
With the growing size and increasing complexity of VLSI circuits,automatic test pattern generation (ATPG) for delay faults is becoming more and more significant.This paper describes a satisfiability (SAT) based ATPG algorithm for transition path delay faults.We discuss how to convert an ATPG problem to a SAT formula where both non-robust and robust test are considered for guiding the test generation for transition path delay faults.Transition path delay faults are commonly tested under non-robust conditions since only small percentage of the transition faults can be detected robustly.However,some small extra delays may cause faulty behavior on a sub-path by their accumulative effect though they do not cause faults by themselves,and the faulty behavior may not be detected under non-robust tests.Here we use a SATbased method to solve the problem.The effectiveness of the algorithm is demonstrated on a set of ISCAS85 benchmarks.
satisfiability automatic test pattern generation (ATPG) transition path delay fault.
Sheng Jiang Weimin Wu
School of Computer and Information Technology Beijing Jiaotong University Beijing,China
国际会议
太原
英文
490-494
2011-02-26（万方平台首次上网日期，不代表论文的发表时间）