Design of Re-triggered Monostable Circuit Using Verilog HDL

摘要：

Specifily introduce the characteristics and the implementation principle of the monostable circuits, and describe the detailed process of design using Verilog HDL.then we use quartus II 9.0 to build a new project. compile the design and create a waveform vector file for simulation, and give the functional simulation waveforms.FinaIly,the project is downloaded to the FPGA hardware board, what we have obtained by running the design has the same results with the functional simulation,which verifies the correctness of the design.

关键词： Monostable Circuiuit Quartus Ⅱ Verilog HDL

作者: CHEN Lian-wen YUAN Fei CHENG En

作者单位: Key Laboratory of Underwater Acoustic Communication and Marine Information Technology (Xiamen University),Ministry of Education Xiamen,China

会议类型: 国际会议

会议名称: 2011 International Conference on Communication and Electronics Information(ICCEI 2011)(2011年通信和电子信息国际会议)

会议地点: 海口

会议语种:英文

页码: 163-166

在线出版日期: 2011-02-22（万方平台首次上网日期，不代表论文的发表时间）