A 10-bit 100MSampIe/s Current-Steering DAC In 0.13um CMOS Process

摘要：

This paper describes a 10-bit 100MS/s currentsteering DAC segmented into 7 MSB unary and 3 LSB binary-weighted cells. A hierarchical symmetrical switching sequence that compensates gradient errors is developed to improve linearity performance. Cascode current source and differential cascode switches with a constant bias voltage can improve the DACs dynamic performance. The DAC is implemented in the mixed-signal 0.13um CMOS process and operates at 2.SV supply for analog circuits and 1.2V supply for digital circuits. The measured results show that the SFDR and ENOB are 67dB and 8.9 bits respectively, and the measured INL and DNL are +/- 0.2LSB and +/- 0.1LSB at a 10-bit level, respectively.

关键词： current-steering DAC segmented high accuracy

作者: Zhou Lingli Huang Jiwei Huang Weichao Li Zhengping Zeng Longyue Ma Chuanhui Wang Yongping

作者单位: Guangzhou Runxin Information Technology Co.,Ltd, Guangzhou, 510663, China Guangzhou Runxin Information Technology Co.,Ltd, Guangzhou, 510663, China Institute of RF-&OE 1C, So

会议类型: 国际会议

会议名称: 2011 International Conference on Communication and Electronics Information(ICCEI 2011)(2011年通信和电子信息国际会议)

会议地点: 海口

会议语种:英文

页码: 76-79

在线出版日期: 2011-02-22（万方平台首次上网日期，不代表论文的发表时间）