The SMS4 Cryptographic System Design based on Dynamic Partial Self-reconfiguration Technology

摘要：

This paper describes SMS4 algorithm by using dynamic partial self-reconfiguration. The design is implemented on Xilinx VirtexII-Pro XC2VP30 FPGA devices. The partial self-reconfiguration encryption/decryption module data throughput is up to 50Mb/s, key expansion and encryption/decryption modules use 1606 and 1570 slices respectively, and the resource utilization ratio of the key expansion by using partial self-reconfiguration technology is less 32.03％ and slices are less 757 than the nonreconfiguration technology. SMS4 implementation gets a good balance between high performance and low complexity in area. The theoretical and practical research of dynamic partial self-reconfiguration has a broad space for development and application prospect.

关键词： dynamic partial self-reconfiguration FPGA SMS4

作者: Wang Jianxin Gao Xianwei Sui Meili Li Xiuying

作者单位: Department of Electronic and Information Engineering Beijing Electronic Science and Technology Insti Beijing Senior Expert Technology Center Chinese Academy of Sciences Beijing, China

会议类型: 国际会议

会议名称: 2011 International Conference on Communication and Electronics Information(ICCEI 2011)(2011年通信和电子信息国际会议)

会议地点: 海口

会议语种:英文

页码: 374-377

在线出版日期: 2011-02-22（万方平台首次上网日期，不代表论文的发表时间）