How Many Entries We Need in Miss Handling Architectures of L1 and L2 Cache?

摘要：

Recently-proposed processor micro-architectures for high Memory Level Parallelism (MLP) harvest substantial performance gains. Unfortunately, MissHandling architectures (MHAs) of current cache hierarchies are too limited to support the requirement of high MLP system. This paper proves the number relation of MHA entries between L1 and L2 cache, presents an algorithm to forecast the supremum of MHA entries. The analysis results present the MHA quantitative requirements for MLP processors. At last we valid the proved relation in experiment.

关键词： Memory-level parallelism Miss-Handling architectures cache memory

作者: De-feng LIU Guo-teng PAN Lun-guo XIE Bin Liu

作者单位: School of Computer National University of Defense Technology Changsha, china

会议类型: 国际会议

会议名称: 2011 International Conference on Information and Computer Networks(ICICN 2011)(2011年信息与计算机网络国际会议)

会议地点: 贵阳

会议语种:英文

页码: 501-504

在线出版日期: 2011-01-26（万方平台首次上网日期，不代表论文的发表时间）