Understanding How Memory-Level Parallelism Affects the Processors Performance

摘要：

As the gap between processor and memory performance increases, performance loss due to long-latency memory accesses become a primary problem. Memorylevel parallelism (MLP) improves performance by accessing memory concurrently. An effective system performance analysis model and method is lacked for these researches. Using queuing theory, we establish a system performance analysis model for MLP. Compared with experimental results, the performance trend of the model is accurate. This model can quickly and accurately characterize the features of the system. The average error rate of model is 12％. This model can effectively introduce the initial MLP system design.

关键词： performance analysis Memory-level parallelism MLP Microarchitecture Multi-core processor

作者: De-feng LIU Guo-teng PAN Lun-guo XIE

作者单位: School of Computer National University of Defense Technology Changsha, china

会议类型: 国际会议

会议名称: 2011 International Conference on Information and Computer Networks(ICICN 2011)(2011年信息与计算机网络国际会议)

会议地点: 贵阳

会议语种:英文

页码: 505-508

在线出版日期: 2011-01-26（万方平台首次上网日期，不代表论文的发表时间）