会议专题

Bottom-up Through Silicon Via (TSV) Filling

There is an increasing demand for electronic devices with smaller sizes, higher performance and increased functionality. The development of vertical interconnects or through silicon vias (TSV) may be one of the most promising approaches to provide the three-dimensional (3D) integration of integrated circuits (IC). It is possible to improve the system s performance with shorter RC delay, shorter signal paths and less power consumption. Electroplating process is one of the major contributors to the cost of TSV. Thus, plating time is one of our major concerns in TSV applications. About 80% of the TSVs are filled with copper due to its high conductivity and wide applications in multilayer wiring. Even though the electroplating of copper for interconnections is well established for the copper damascene microfabrication process, it has been shown that the filling of TSVs with copper plating is a different situation due to the much larger dimensions of TSVs. Generally the filling mechanism consists of conformal plating and bottom up plating. A 100% bottom up filling is In this study, the void free copper filling TSVs with diameter from 10-30 μm and depth from 50-150 μm will be investigated by copper electroplating. A near 100% bottom up plating formula was achieved by Shanghai Sinyang additives in order to achieve void free and seam free filling. Filling performance of this plating formula was evaluated by examining vertical cross-sections and top-down cross-section of the filled TSVs using optical microscope and X-ray method. Pretreatment process and relationship with diffusion time will be also studied with respect to the TSV plating process. The effect of concentration of copper, acid and additives will be optimized to achieve the desired bottom up plating process. The ultimate goal is to achieve TSV plating with shorter plating time and better consistency. Preferred for copper filling in TSV. A seam may exist in via if the majority of filling mechanism is conformal plating. Thus, the bottom up filling profile is one the critical points to achieve void free filling.

Han YU

Sinyang, China

国际会议

2011 12th International Conference on Electronic Packaging Technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

上海

英文

1

2011-08-08(万方平台首次上网日期,不代表论文的发表时间)