Reliability Modeling of Silicon or Glass Interposers to Printed Wiring Board Interconnections
Trend towards ultra-miniaturization of packages and systems has necessitated the use of high I/O interposers or packages made of either silicon or glass 1. However, both of these materials have low coefficient of thermal expansion (CTE) compared to organic boards, thereby raising interconnection reliability concerns when assembled directly on the organic system boards. This paper presents an approach to address these reliability problems by using novel build-up dielectrics with low Youngs Modulus to reduce the strains induced in the solder ball interconnections to the board. This proposed approach is compatible with surface mount technology and also helps the handling and metallization of thin silicon/glass substrates. Finite element method has been used to analyze the effectiveness of the compliant dielectrics, laminated onto silicon or glass substrates. Parametric study has been performed to analyze the influence of material properties and geometry parameters on the reliability of the SMT interconnections.
Xian Qin Nitesh Kumbhat Venky Sundaram Rao Tummala
Packaging Research Center, Georgia Institute of Technology 813 Ferst Dr NW, Atlanta, GA 30332
国际会议
上海
英文
12-16
2011-08-08（万方平台首次上网日期，不代表论文的发表时间）