Finite Element Stress Analysis of 3D TSV Stack Subject to Large Temperature Loading

摘要：

As multiple layers of planar device are stacked to alleviate signal delay problem and reduce chip area, Through silicon via (TSV) is introduced to replace the large number of long interconnects needed in previous 2D structure. However, the thermal-mechanical reliability problems of TSVs, such as interfacial delamination, via cracking and so on, have become a serious reliability concern. In this paper, finite element method (FEM) was employed to analyze the thermal-mechanical behavior of 3D-TSV stacks on different substrates. The thermal-mechanical response of 3D TSV stack using underfills is also investigated. It is found that the stress profile varies with geometric parameters such as edge distance and via diameter, while the underfills and substrate materials also have a significant effect.

作者: Zhiyuan Zhu Wenping Kang Yang He Yunhui Zhu Min Yu Min Miao Jing Chen Yufeng Jin

作者单位: National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij

会议类型: 国际会议

会议名称: 2011 12th International Conference on Electronic Packaging Technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

会议地点: 上海

会议语种:英文

页码: 32-35

在线出版日期: 2011-08-08（万方平台首次上网日期，不代表论文的发表时间）