Process Development of Multi-layer Stacked Chip Module

摘要：

In this paper, at first electroplating of copper and tin is optimized to fabricate micro-bump. Chip-to-chip bonding process is developed. Then, a temporary bonding process is developed and verified by experiment. And finally, a process for manufacturing multiple layer stacked chip module is designed and prototype of a 4 layer stacked chip module is fabricated successfully.

作者: Shenglin Ma Xin Sun Yunhui Zhu Wenping Kang Qinghu Cui Min Miao Jin Chen Yufeng Jin

作者单位: National Key Laboratory on Micro/Nano Fabrication technology, Peking University, Beijing, China, , 1 Shenzhen Graduate school, Peking University, Shenzhen, China, 518055 National Key Laboratory on Micro/Nano Fabrication technology, Peking University, Beijing, China, , 1 National Key Laboratory on Micro/Nano Fabrication technology, Peking University, Beijing, China, , 1 National Key Laboratory on Micro/Nano Fabrication technology, Peking University, Beijing, China, , 1

会议类型: 国际会议

会议名称: 2011 12th International Conference on Electronic Packaging Technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

会议地点: 上海

会议语种:英文

页码: 118-120

在线出版日期: 2011-08-08（万方平台首次上网日期，不代表论文的发表时间）