Test Structure Designed for Vias in Multi-layer Package Substrate

摘要：

A symmetrical test structure for the measurement of vias in multi-layer package substrate was put forward in this paper. Based on the known S-parameters of this designed symmetrical structure and the deduced expressions, an indirect method to get the actual S-parameters of a single via was presented. In order to verify the validity of the proposed method, the simulation models were built in Power SI environment from SIGRITY. After a comparison between the simulated and calculated results, the correctness of the proposed method was proved.

作者: Sun Ling Yang Ling-ling Sun Hai-yan Wang Shenglong

作者单位: Jiangsu Key Laboratory of ASIC Design, Nantong University, Nantong, China

会议类型: 国际会议

会议名称: 2011 12th International Conference on Electronic Packaging Technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

会议地点: 上海

会议语种:英文

页码: 445-447

在线出版日期: 2011-08-08（万方平台首次上网日期，不代表论文的发表时间）